Research Interests

• Radiation Effects Modeling in Integrated Circuits
• Circuit Level Soft Error Hardening
• Low Power Design & Reliability Analysis
• Interconnect Modeling and Noise Prediction
• Crosstalk Delay Modeling and Prediction
• Contactless VLSI Testing

Current Research Projects

• "Thermal-Aware Hardening for Advanced CMOS Circuits”: Thermal effects have important implications for both performance and reliability of chips. If the impact of temperature is not taken into consideration, the mitigation efforts may fail which would lead to a significantly greater reliability issue for advanced technologies. For military applications, the effects can be much worse since  the integrated circuits needs to function over a wide range of temperatures ranging from -55℃ to 125 ℃. By identifying the impact of of thermal effects, design principles will also be developed for other radiation hardening methodologies currently being used in avionics and space and military applications which will greatly benefit the industry.

• "Modeling the Impact of Temperature on Single-Walled Carbon Nanotube Interconnects": Carbon nanotubes (CNTs) are graphene sheets rolled up into cylinders with diameter of the order of a nanometer.. By using CNT bundles overall resistance is reduced and it enables CNT based interconnect to replace conventional copper interconnects at advanced VLSI technology nodes. Several studies have investigated the electro-thermal transport in metallic SWCNTs for the applications of interconnect. Researchers have compared the performance of CNT-bundle interconnects to that of copper interconnects and found that there were significant performance improvements for intermediate and long interconnects. In our research, the crosstalk noise between SWCNT bundle interconnects with temperature independent and thermally aware model will be investigated.   We will  develop an efficient computational model for crosstalk estimation in identically coupled SWCNT bundle interconnects.

• "Design of Asynchronous Circuits for Robustness in Deep Submicron CMOS Circuits": As the conventional CMOS scales down, the combinational logic will become susceptible to soft errors.. A more robust solution would be the use Asynchronous Circuits for soft errors and for process, supply voltage, and temperature variations. In this project, the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance will be investigated. The behavior of Null Convention Logic (NCL) circuits in the presence of particle strikes will also be analyzed.

• “Radiation tolerance of Various Circuit Design Styles”

External Funding Received:

• Sayil, S.  PI, Myler, H. R. Co-PI,  “Space Radiation Effects on Technology and Human Biology and Proper Mitigation Techniques”, NASA/ Texas Space Grant Consortium (TSGC) Higher Education, March 2008, September 2008-August 2010, $15,000
• Sayil, S., PI, (no co-PI), “Low Power Radiation Tolerant VLSI Design for Advanced Spacecraft”, Texas Space Grant Consortium (TSGC) / NASA New Investigations Program (NIP), October 2010, PI, $9,000.
• Sayil, S., PI, (no co-PI), "Project Title: Enhancing Student Learning via Value Added Engineering Education (VAEE)",  Academic Partnerships, Fall 2015, Funding Period: 11/20/2015- 6/30/2016- $4,116.